The design and manufacture of very large scale integration (VLSI) integrated circuit devices continue to become more complex and sophisticated. Current VLSI technology allows for the design and manufacture of large-area integrated circuits with sub-micron feature sizes, such that millions of devices can be placed on a single chip. Even using the highest level of control in state-of-the-art technology, a fabrication process only provides control of transistor characteristics to a given range, generally a Gaussian distribution, and is not able to provide precise control to specific characteristic values. Such process gradients occur not only within a single batch of wafers, but exhibit themselves across a single wafer as well. VLSI design libraries typically are characterized using the extremes of the process distribution, referred to in the industry as the “slow” and “fast” process corners. A “typical” process corner corresponding to the center of the process distribution often also is provided.
Ideally, it would be desirable to know the process corner for each individual die. Since such knowledge to this point is impractical for large-scale device manufacture, VLSI design addresses the worst operating conditions, or slowest process corner. By choosing a design for the slow process corner, the designers can be sure that the typical and fast process corners will still work with that single design. If the designers were to choose a design that was optimal for typical or fast process corners, then those die corresponding to slow process corners might hot operate properly, resulting in lower yields and higher cost per device.
A downside to such an approach, however, is that all die then operate as if those are from the slowest process corner. If a particular die is not at the worst process corner, then the chip likely is operating at a lower frequency than is otherwise possible. Increasing the frequency would result in improving the performance of the chip. The chip also may be operating at a higher voltage than is necessary to meet timing, which results in unnecessary power usage. Unnecessary power usage is becoming evermore important as chips are increasingly used in portable devices that run from battery power.
Today, there are means to adaptively adjust the operating needs of a chip regardless of the process corner of that chip. In one such process, an advanced process power controller is used to detect a slack in critical timing. If the critical path timing has not reached a maximum, the voltage can be lowered to provide power savings. This closed loop method requires a lot of characterization collaterals to make the approach work. A simpler process that quickly and cheaply provides process corner information is desired.